1. Field
The present invention generally relates to semiconductor design and manufacturing. More specifically, the present invention relates to a method and a system for accurately calibrating a photolithography process model based at on a process window parameter.
2. Related Art
Semiconductor manufacturing technologies typically include a number of processes which involve complex physical and chemical interactions. Since it is almost impossible to find exact formulae to predict the behavior of these complex interactions, developers typically use process models which are fitted to empirical data to predict the behavior of these processes. A semi-empirical process model can be used in a number of applications during the design of a semiconductor chip.
For example, in a technique which is referred to as “Optical Proximity Correction” (OPC), a photolithography model is used to make corrections to a semiconductor chip layout (chip layout) to compensate for undesirable optical and resist effects of a photolithography process. Hence, a photolithography model typically also includes an aerial image model which models aerial image formation, and a resist model which models resist image formation.
During a photolithography process, the optical exposure system and the wafer surface are configured so that an in-focus aerial image of the layout can be formed on the surface of the wafer. However, an aerial image does not always form under ideal in-focus conditions. For example, as a result of topography variations across the wafer, aerial images of some layout features may form some distance away from the in-focus condition, which is referred to as a “defocus” condition. The range/span of defocus around an in-focus condition which does not cause the manufacturing results to go out of the design specifications is often referred to as a “process window.”
An accurate photolithography model should provide an accurate aerial image model which can correctly model the defocus conditions and process model for different layout features, in particular at advanced technology nodes (e.g., 32 nm or below). At the advanced technology nodes, critical dimension (CD) control requirement becomes significantly tighter. For example, at such advanced technology nodes, Across-Chip Linewidth Variation (ACLV) is required to be less than 4 nm, which significantly reduces the process window.
However, because of the difficulty in collecting process window data, conventional photolithography modeling techniques typically only use nominal process condition data which is collected under a single focus condition. Unfortunately, a photolithography model calibrated only using nominal process conditions cannot predict the correct defocus and/or image depth values. Moreover, a calibrated lithography model based only on nominal data cannot be separated into an aerial image model which describes the optical effects, and a resist model which describes the resist effects. However, such separation is necessary for source map optimization (SMO) applications. On the other hand, existing photolithography models which are calibrated using various defocus data are often degraded by significant metrology noise in the defocus data. These models still cannot predict correct process windows, because the model-fitting parameters are affected by the noisy defocus data.
Hence, what is needed is a technique for accurately calibrating a photolithography model without the above-described problems.